1. Field of the Invention
The present invention relates to a signal processing circuit used in a digital serial interface.
2. Description of the Related Art
In recent years, as an interface for transfer of multimedia data, the IEEE (Institute of Electrical and Electronic Engineers) 1394, High Performance Serial Bus for realizing high speed data transfer and real time transfer has become the standard.
The types of data transfer of this IEEE 1394 serial interface include asynchronous transfer for requests, requests for acknowledgement, and confirmation of reception of the related art and isochronous transfer with which the data is sent at one time from a certain node at 125 .mu.s.
In this way, with an IEEE 1394 serial interface having such two transfer modes, data is transferred in units of packets.
FIGS. 11A and 11B are views of the byte size of a source packet in isochronous communication. FIG. 11A shows the size of a packet in the digital video broadcast (DVB) method; while FIG. 11B shows the size of a packet in the digital satellite system (DSS) method.
The source packet in the DVB method is comprised of 192 bytes, that is, 4 bytes of a source packet header (SPH) and 188 bytes of inherent transport stream data (TSD), as shown in FIG. 11A.
Contrary to this, the source packet in the DSS method is comprised of 144 bytes, that is, 4 bytes of a source packet header (SPH), 10 bytes of additional data (AD0 to AD9), and 130 bytes of inherent transport stream data (TSD) as shown in FIG. 11B.
The additional data is inserted between the source packet header and the transport stream data. Note that, in the IEEE 1394 standard, the unit of minimum data that can to be handled is one quadlet (=4 bytes=32 bits), therefore the transport stream data and the additional data must be set to be able to be comprised in total of 32 bit units.
Note that at the default, no additional byte is set.
FIG. 12 is a view of an example of a correspondence between the original data when data is transmitted in the isochronous communication of the IEEE 1394 standard and the packets actually transmitted.
As shown in FIG. 12, each of the source packets of the original data is given a source packet header of 4 bytes and padding data for adjusting the data length and then is divided into a predetermined number of data blocks.
Note that since the unit of data when transferring a packet is one quadlet (4 bytes), the byte lengths of data blocks, various headers, etc. are all set to multiples of 4.
FIG. 13 is a view of the format of the source packet header.
As shown in FIG. 13, in 25 bits in the source packet header is written a time stamp utilized for suppressing jitter when for example MPEG (Moving Picture Experts Group)-TS (Transport Stream) data utilized in a digital satellite broadcast etc. of the above DVB method is transmitted by isochronous communication.
Such a packet header, a common isochronous packet (CIP) header, or other data is then added to a predetermined number of data blocks so as to produce the final packets.
FIG. 14 is a view of an example of the basic configuration of an isochronous communication use packet.
As shown in FIG. 14, in a packet for isochronous communication, the first quadlet is comprised of a 1394 header, the second quadlet a Header-CRC, the third quadlet a CIP-header 1, the fourth quadlet a CIP-header 2, the fifth quadlet a source packet header (SPH), and the sixth quadlet and subsequent quadlets the data regions. The final quadlet is a Data-CRC.
The 1394 header is comprised by a "data-length" representing the data length, a "channel" indicating number of the channel (one of 0 to 63) transferred through this packet, a "tcode" representing a code of processing, and a synchronous code "sy" prescribed by each application.
The Header-CRC is an error detection code of the packet header.
The CIP-header 1 is comprised by a source node ID (SID) region for the transmission node number, a data block size (DBS) region for the length of the data block, a fraction number (FN) region for the number of divisions of the data in the formation of the packet, a quadlet padding count (QPC) region for the number of the quadlets of the padding data, a source packet header (SPH) region for the flag showing the existence of the source packet header, and a data block continuity counter (DBC) region for the counter for detecting the number of isochronous packets.
Note that the DBS region shows the number of the quadlets transferred through one isochronous packet.
The CIP-header 2 is comprised by an FMT region for the signal format showing the type of the data to be transferred and a format dependent field (FDF) region utilized corresponding to the signal format.
The SPH header has a time stamp region in which is set a value obtained by adding a fixed delay value when the transport stream packet.
Further, the data CRC is the error detection code of the data field.
The signal processing circuit of the IEEE 1394 serial interface for the transmission and reception of packets having the above structure is mainly constituted by a physical layer circuit for directly driving the IEEE 1394 serial bus and a link layer circuit for controlling the data transfer of the physical layer circuit.
In the isochronous communication system in the IEEE 1394 serial interface, as shown in for example FIG. 15, the link layer circuit 2 is connected to an application, that is, MPEG transporter 1, while the link layer circuit 2 is connected to a serial interface bus BS via a physical layer circuit 3.
In the transfer of data of the IEEE 1394 serial interface, the transmission data and reception data are stored once in a storage device such as a first-in first-out (FIFO) memory (hereinafter simply referred to as an FIFO) provided in the link layer circuit 2. In actuality, an asynchronous packet use FIFO and an isochronous packet use FIFO are separately provided.
As shown in FIG. 11, however, the size of a source packet of a normal MPEG transport stream is changeable, for example, 192 bytes in the DVB and 144 bytes in the DSS.
On the other hand, the size of the FIFO provided in the link layer circuit is set. Therefore, when there is an error in the source packet which is received, it may be considered to propagate the error around the FIFO by providing a register with several consecutive error bits separate from the FIFO.
In this case, however, a separate circuit has to be provided to make it known which source packet stored in the FIFO the error bit is for. This has the disadvantage that the size of the circuit becomes larger.
Further, when using isochronous communication to transmit MPEG-TS data used in the above-mentioned DVB system or other digital satellite broadcasting, the signal processing circuit on the reception side must output transport stream data to the so-called application side that is, the MPEG transporter, based on the time side by the time stamp added to the packet.
In current IEEE 1394 serial interface signal processing circuits, however, no processing system has yet been established for the time stamp added to the received packet.
For example, the case may be considered where an unpredictable value of the time stamp not possible is set and transmitted due to blurring of data or the connection of different systems. It is consequently necessary to establish a system which can operate stably without stopping even in this case.
Further, it is necessary to realize a circuit which can output a packet immediately after a time set for the application side or reception.
Further, when using isochronous communication to transmit MPEG-TS data used in the above-mentioned DVB system or other digital satellite broadcasting, the transmission side signal processing circuit adds a delay in accordance with the amount of data to the time stamp to be added to the packet.
This delay is set to a small value when the amount of the image or other data increases. The reception side outputs transport stream data to the so-called application side, that is, the MPEG transporter.
The reception side stores the received data once in an FIFO or other storage device. The smaller the delay set in accordance with the amount of data at the transmission side, the shorter the time from reception to when the transport stream data to the MPEG transporter is output.
As explained above, however, since there is no system for processing the time stamp added to the packet in current IEEE 1394 serial interface signal processing circuits, when for example the channel is changed and the amount of data increases, unnecessary data ends up being output to the application side regardless of the change of the channel. Alternatively, while the data with a large delay of a time stamp before the change of channel is being stored in the FIFO without being output yet from the reception side, there is the danger that the next data with a small delay will be stored in the FIFO, the positional relationship of the data will be ruined, and overflow or other problems will occur.